FIG. 41 illustrates an example of the arrangement of a receiving device of an optical line terminal (to be referred to as an OLT hereinafter) of PON (Passive Optical Network) system which has been developed as a means for implementing FTTH (Fiber To The Home). The OLT stores a plurality of optical network units (to be referred to as ONUs hereinafter) (not shown). According to the IEEE 802.3av standard, up link signals from the ONUs to the OLT are time-divisionally multiplexed as burst signals having different strengths or phases for the respective ONUs.
As shown in FIG. 41, the receiving device of the OLT includes an optical receiving device 200, a CDR (Clock Data Recovery) circuit 201, a demultiplexer 202, and a control LSI 203. The optical receiving device 200 includes an APD (Avalanche Photodiode)-TIA (Transimpedance Amplifier) 204 and a LIM (Limiting Amplifier) 205. The APD-TIA 204 converts an optical signal into a current signal and further converts the current signal into a voltage signal. The LIM 205 amplifies the voltage signal while limiting its amplitude to a level identifiable/recoverable by the CDR circuit 201 of the subsequent stage. The control LSI 203 includes a low-speed receiving circuit 206.
The receiving device of the OLT shown in FIG. 41 causes, for each burst signal, the optical receiving device 200 to perform gain control and threshold detection and the CDR circuit 201 to perform clock extraction and signal retiming. The demultiplexer 202 demultiplexes the multiplexed signal output from the CDR circuit 201 into N outputs. The control LSI 203 having a MAC (Media Access Control) function then performs necessary processing, thus complementary signal reception processing. To improve the up link transmission efficiency from the ONUs to the OLT, the necessary overhead (preamble period) needs to shorten, and the optical receiving device 200 or the CDR circuit 201 having a quick response characteristic to the burst signal is necessary. The CDR circuit 201 of this type is disclosed in, for example, J. Terada, et al., “Jitter-reduction and pulse-width-distortion compensation circuits for a 10 Gb/s burst-mode CDR circuit”, in 2009 IEEE International Solid-State Circuits Conference Digest, pp. 104-106, February 2009.
The recent progress of CMOS technologies is making the control LSI capable of integrating not only a logic circuit but also a high-speed I/O (for example, CDR circuit) and the like. However, equipping an LSI with a CDR circuit of special specifications for burst signals is not beneficial in terms of both cost and technique. To enable the control LSI to process a burst signal, conventionally, the demultiplexer 202 needs to parallelly expand the data signal at a low speed so as to permit the phase change of a clock extracted by the CDR circuit 201, as shown in FIG. 41. In this arrangement, since both the CDR circuit 201 and the control LSI 203 need to include buffers as many as the parallel paths, power consumption increases. In addition, the size of the device increases due to make the wires of the parallel paths isometric.
On the other hand, to directly input serial data signals to a control LSI including a general-purpose CDR circuit compatible with a continuous signal, the CDR circuit compatible with a continuous signal needs to be prevented from unstably operating due to frequency step-out or the like. FIG. 42 illustrates an arrangement disclosed in Japanese Patent Laid-Open No. 3-166836 as a technique of this type. A signal multiplexing device shown in FIG. 42 includes a flip-flop circuit (to be referred to as an F/F hereinafter) 3 and a PLL-type clock recovery circuit 30. The clock recovery circuit 30 includes a phase comparator 31, a low pass filter (to be referred to as a LPF hereinafter) 32, a voltage controlled oscillator (to be referred to as a VCO hereinafter) 33, and a selector 34.
FIGS. 43A to 43E are timing charts for explaining the operation of the signal multiplexing device. The phase comparator 31 compares the phase of input data 4 with that of a recovered clock 7, and outputs a phase difference signal representing the phase difference between the input data 4 and the recovered clock 7. The LPF 32 integrates the phase difference signal and thus converts it into a control signal. The VCO 33 outputs a recovered clock 35 having a frequency corresponding to the voltage of the control signal. The selector 34 selects the recovered clock 35 in a normal state in which the input data 4 is input, and outputs it as the recovered clock 7. In this way, the recovered clock 7 having the same frequency as the input data rate frequency can be generated.
The recovered clock 7 is input to the clock terminal of the F/F 3 and used for retiming of the input data 4 input to the data input terminal of the F/F 3. The F/F 3 thus outputs recovered data 6.
On the other hand, when a no-signal state has occurred due to loss of the input data 4, the selector 34 selects an IDLE signal 36 that is the complementary signal of the input data 4 in accordance with a switching signal 37. To always stabilize the operation of the PLL even when the input data 4 is intermittently lost, the IDLE signal 36 having almost the same frequency as the recovered clock 35 output from the VCO 33 is multiplexed and input to the clock recovery circuit 30 in the loss period (no-signal period). This stabilizes the operation of the clock recovery circuit 30, as shown in FIG. 43D.